Current memory circuits that use double data rate (DDR) and quadruple data rate (QDR) access schemes have separate address, write data, read data and status pins. These access schemes require high frequency data transmission links that provide low bit error rate (BER), high bandwidth and low on-chip latency. Bandwidth is the amount of information exchanged during read and write operations. Latency is the time lapsed between an event in an input signal and a corresponding event in an output signal that results from the event in the input signal. For example, in a memory circuit latency is the time lapsed between the receipt of a ‘Read’ command at an input pin of the memory circuit and the transmission of the corresponding read data to the output pins of the memory circuit.
In a device that has a serial transmission link one or more serializer-deserializer (SERDES) circuits convert data packets between serial and parallel formats. It is common practice to place the SERDES circuits and other associated logic components along the periphery of the silicon chip. Such architecture results in a wide spread in latencies in the silicon, depending on the distance between the SERDES and the specific functional block that is the source or the destination of the data. Thus, worst case timing latency is determined by the longest path set by the I/O which is the furthest away from any one device resource. A typical layout of I/O at the periphery would result in the worst case path from one corner of the die to the opposite corner. The resulting distance that an input signal must traverse could be the width plus the height of the die.
Error rates are expected to increase for high speed data links. Many circuits have a cyclic redundancy check (CRC) circuit to perform error checking on data packets. Error checking is performed across the entire data packet, which may be striped across multiple data lines to increase bandwidth and to reduce latency. However, such an approach requires that multiple data lines converge into the CRC circuit to allow error checking, thus adding to the length of the traces that signals must traverse for an operation.
Moreover, heaviest packet traffic in a device typically occurs as communication among functional blocks formed in or on the silicon substrate. Data lines formed in or on the silicon substrate are dimensionally constrained, thus representing significant capacitive and resistive loads to the paths the signals must traverse. In addition, communication lines in or on silicon further need to circumvent the functional blocks that create barriers to signal routing, adding to the lengths of the communication lines. As a result, on die packet traffic routed through communication lines on a silicon substrate with a significant density of functional blocks will experience increased latencies.
In an application using a SERDES circuit, placement of a power pin next to a data pin in a package substrate complicates “signal escape” to an external component. Routing signals in a printed circuit board from a signal pad at the center of the chip through a “picket fence” of power pins exposes the data signal on the signal pad to interference, cross-talk, and distortion. Thus packages where the signal pins are toward the outer edges of the packet reduce the picket fence effect. To overcome the above problem, it is customary to place I/O signals at the edge of the silicon substrate. However such placement can negatively impact the overall latency of the circuit. Package pin-out configuration is a concern in integrated circuit design.
Tx/Rx differential pairs are typically grouped closely together in high speed communication systems. Each Tx transmitter includes a transmit channel that conveys read data and status information out of a package. Each Rx receiver includes a receive channel that receives address, control and write data from outside of the package. In networking devices, the proximity of Tx and Rx channels can result in data crosstalk and an increase in bit flips.
Bandwidth becomes more significant when a SERDES block is combined with a high speed memory block. Due to the proximate locations of Tx to Rx, conventional systems have a significantly limited signal line density, which adversely affects the available bandwidth. In high speed communication systems, it is increasingly critical to have a significant amount of line/signal density for improving the device bandwidth.
U.S. Pat. No. 7,405,946 to Hall et al. (“Hall”) separates transmitter contacts from receiver contacts in a high speed interface pattern. However, Tx data channels in Hall's pattern must be positioned parallel to Rx data channels to convey data from the transmitter out to the host. Parallel Tx/Rx channels tend to degrade data signals and increase error rates. In Hall's Tx/Rx pattern, the data line transporting a high speed Tx signal must cross over an Rx data line before exiting the PC board. Such proximity of Rx contacts to Tx contacts contributes to noise coupling between Tx and Rx signals. Thus, Hall does not resolve the problem of Inter Signal Interference (ISI) for high speed data links.
Accordingly, there is a need for an IC device layout that takes into account the routing delay for high speed data signals on a PCB or a SOC. In addition, a need exists for simplified data path routing for high speed networking devices to minimize the routing length through the silicon die. Further, a need exists for reducing the amount of interference between Rx and Tx signals while easing printed circuit board layout.